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verilogfpgabitparity

Combine 1 bit inputs into single register appropriately

I am programming in verilog and I have a series of 1 bit inputs - say:

input SIGNALP,
input SIGNAL1,
input SIGNAL2,
input SIGNAL3,
input SIGNAL4,
input SIGNAL5,
input SIGNAL6,
input SIGNAL7

I then want to combine these bits into an 8 bit register, where the first bit is the parity bit (SIGNALP), the second bit is SIGNAL1, the second is SIGNAL2, etc. How can I do this? Adding all of these, for instance, wouldn't work, as it wouldn't recognize the place value of these. The reason I'm doing it this way is because parallel data is faster than serial data. Any help would be appreciated. Thanks!

Solution

  • It seems you want to concatenate these bits into a new register

    wire [0:7] my_new_register;
assign my_new_register = {SIGNALP, SIGNAL1, ... SIGNAL7}; // you fill in ...

    You didn't specify how you wanted each pin to be mapped into the new signal, so you will have to adjust this to suit your needs.