hierarchical compile order with modelsim on command line

Question

I'm trying to compile a VHDL design with modelsim on command line. Is there any way to get an automatical compile order according to the design hierarchy?

I didn't find an option in the documentation of vcom. Only link I found is this, where the solution was to write a brute force script. But it's 10 years ago, so maybe there is anything new. It should be like the option -i of ghdl.

I'm using Altera/Intel Modelsim 18.0 on Linux.

Answer 1

VUnit is an open source tool that will that for you. I recommend the following reading

1. Installation
2. Compilation (what you're looking for)

Disclaimer: I'm one of the authors