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riscvrocket-chip

Rocket-chip instruction trace columns


When I run make run-asm-tests in the emulator directory of rocket-chip, I get a bunch of *.out files in the emulator/output directory. These appear to be instruction traces but the columns are not labeled. I was wondering what each of these columns means. Thanks!

For Example:

C0:      82212 [0] pc=[000000081c] W[r 0=0000000000000400][0] R[r 8=0000000000000000] R[r 0=0000000000000000] inst=[40044403] lbu     s0, 1024(s0)
C0:      82213 [0] pc=[000000081c] W[r 0=0000000000000400][0] R[r 8=0000000000000000] R[r 0=0000000000000000] inst=[40044403] lbu     s0, 1024(s0)
C0:      82214 [1] pc=[0000000820] W[r 8=0000000000000000][1] R[r 8=0000000000000000] R[r 3=0000000000000003] inst=[00347413] andi    s0, s0, 3
C0:      82215 [1] pc=[0000000824] W[r 0=0000000000000000][0] R[r 8=0000000000000000] R[r 0=0000000000000000] inst=[fe0408e3] beqz    s0, pc - 16
C0:      82216 [1] pc=[0000000814] W[r 8=0000000000000000][1] R[r 0=0000000000000000] R[r20=0000000000000003] inst=[f1402473] csrr    s0, mhartid

Solution

  • The first column C0: stands for core 0. If you have multiple cores each will print its own trace prefixed with its hartid.

    The second column 82212 through 82216 is the current cycle number.

    The third column [0] or [1] shows whether this instruction committed this cycle (i.e. finished without exceptions).

    The fourth column pc=[...] shows the current program counter value.

    The fifth column W[r 8=...][1] shows the destination register of the current instruction in the suffix of the r, the value being written to that register after the =, and whether this write is happening in the [0] or [1].

    The sixth column R[r 8=...] shows the the first source register's index in the suffix of the 'r and the value read from that register after the =.

    The seventh column is the same as the sixth but for the second source register.

    The eighth column inst=[...] shows the bits in the current instruction.

    The ninth and final column shows a disassembly of the current instruction.