I am trying to initialize a multi dimensional parameterized array in SystemVerilog which I have described as below:
...
parameter INPUT_WIDTH = 16;
parameter NUM_ELEMENTS = 4;
...
reg signed [INPUT_WIDTH-1 : 0 ] ss_res_reg[NUM_ELEMENTS-1:0];
I want to initialize the ss_res_reg
to zero on every falling edge of rst
so:
always_ff @(posedge clk or negedge rst) begin
if(~rst) begin
ss_res_reg <= '{NUM_ELEMENTS{NUM_ELEMENTS{1'b0}}};
end else begin
ss_res_reg <= ss_res;
end
end
The problem is with this line ss_res_reg <= '{NUM_ELEMENTS{INPUT_WIDTH{1'b0}}};
. If I change it to ss_res_reg <= '{NUM_ELEMENTS{16'b0}};
it works perfectly fine. However, when I want to use the INPUT_WIDTH
parameter, Xilinx tool gives me the following error: syntax error near {
. I also tried ss_res_reg <= '{NUM_ELEMENTS{16{1'b0}}};
and got the same error. Does anyone know what am I doing wrong?
The error lies in the fact that you can not replicate unpacked array elements.
There is a simple solution:
if(~rst)
for (integer i=0; i<NUM_ELEMENTS; i++)
ss_res_reg[i] <= {INPUT_WIDTH{1'b0}};