I am trying to setup a virtual address mapping with 2 levels of indirection for a Cortex-A v8 64bit in Baremetal. Page Table level 2 will contain Table descriptors and page Table level 3 will contains the block entries.
By looking at the documentation for the 64KB pages: http://infocenter.arm.com/help/topic/com.arm.doc.den0024a/ch12s03.html#BABIIEFG
I don't understand how the size of the "Level 2 index" and "Level 3 index" are computed and if I need to follow the same way. In this example, table 2 has 8192 entries (so 13 bits are needed) and table 3 is addressed using 13 bits. Is is possible to change the size of the "Level 2 index"? How can I know the size of the index if I have 3 levels of indirection?
First of all, here is a general description about ARMv8 page table design.
The index bits(9 bits, 11 bits, and 13 bits) are fixed for different page size (4kb, 16kb, and 64kb). The details about the bits information can be found in the link above. If you are using 3 levels page table then it should be 16kb page granule and the corresponding index bits of each level are 11.
Finally, here is the answer I posted before to explain the AArch64 page table walk. Maybe it's helpful for you to understand the ARM page table.