Good evening, I'm trying to implement a 8 bits full adder in vhdl, but for that I need to use eight complete 1-bit full adders. I know how to do the 8bits full adder, but I don't know how to use the eight 1bit full adder. I have this code:
library IEEE;
use IEEE.std_logic_1164.all;
entity onebitfulladder is
port (num1, num2, carry_in : in std_logic;
result, carry_out : out std_logic);
end onebitfulladder;
architecture behavior of onebitfulladder is
signal S1, S2, S3 : std_logic;
begin
result <= num1 xor num2 xor carry_in;
S1 <= num1 and num2;
S2 <= num1 and carry_in;
S3 <= carry_in and num2;
carry_out <= S1 or S2 or S3;
end behavior;
Basically, I need to use 1-bit adders to implement a full 8-bit adder. I've implemented the full 1 bit adder, but I do not know how to use it to form an 8 bit adder.
Lets call the code you gave "onebitfulladder". You should have a VHDL file onebitfulladder.vhd
You will want to create a new file "eightbitadder" where you declare and instantiate the component "onebitfulladder".
There are lots of tutorials explaining how to create components in VHDL: https://www.ics.uci.edu/~jmoorkan/vhdlref/compinst.html
Then you can create the eightbitadder by instantiating 8 onebitfulladder