System Verilog subtraction removing important bits
I have a simple subtraction of two 32-bit numbers which I know will never result in a number larger then 25-bit. After elaborating my design is see that the tool (Xilinx Vivado 2018.1) has trimmed the input registers down to 25-bit which will cause incorrect values to be calculated.
logic [31:0] ain;
logic [31:0] bin;
logic [24:0] cout;
assign cout = ain - bin;
this results in an elaborated design with an rtl_sub like this...
After referencing the LRM and some other questions on the subject I feel that this should work by subtracting the two larger numbers and then truncating the result but maybe I am misunderstanding the coding rules?
I additionally tried this which also did NOT work
assign cout = 32'(ain - bin);
Can someone please recommend the most appropriate way to code this?
2's complement subtraction
C = A -B
is the same as
C = A + ~B + 1
There's no way bits [31:25] can have an affect on the result of bits [24:0]. Maybe your assumption about the answer fitting in 25 bits is incorrect.
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