self-defined type cast to string in VHDL

Question

I created a VHDL package with a new type as you can see below:

package useOfLength is

    type length1 is range -(2**31-1) to 2**31-1
    units
        um;
        mm = 1000 um;
        cm = 10 mm;
        m = 100 cm;
        inch = 25400 um;
        yard = 914400 um;
        foot = 304800 um;
    end units;

end;

in my testbench I am trying to "report" the variable "output" of a signal of type length1:

report "The result is " & to_string(output);

Modelsim gives me the following error message:

** Error: G:/OneDrive - Office/SS2018/DRS/exercise6/1106ex03/ex03_tb.vhd(49): (vcom-1136) Unknown identifier "to_string".

I tried a lot (cast to integer and then to string) and also other ways, but nothing is working. I also found casts on the internet, but only for already given types, not for self-defined types. I am also new to VHDL and maybe this is a stupid question...

Answer 1

okay, I found out, that a physical type is the same as an integer...

so to convert it to a string is working like this:

length1'image(output);