How can I implement a sequence generator using a universal shift register?

Question

How can I implement a sequence generator that generates the following sequence

0000 1000 0001 0011 0110 1101 1110 1111

using a universal shift register? The shift register I need to use is the 74LS194 model shown below where the inputs S1, S0 controls the shift mode.

If (S1,S0) = (0,0), then the current value is locked to the next state. If (1,0), it's shift to right. If (0,1), it's shift to left, and (1,1) indicates parallel loading from the parallel data inputs.

I think this would be a simple question if the requirement was just using flip flops of my choice and not the shift register, but with this requirement I don't know where to start. Even though I draw 4 Karnaugh maps for each digit I don't seem to grasp a clue. Any help would be appreciated. Thanks in advance!

Universal shift register 74LS194:

---

Edit: I took the advice and wrote the next state table with the input signals. I noticed that there were too many input variables to consider when I drew the next state table. You have to consider the Qd Qc Qb Qa, CLR, S1, S0, RIn, LIn signals for each next state Qd, Qc, Qb, Qa, which means a 9 variable Karnaugh map for each Q, which I know is ridiculous. Am I missing something here?

Answer 1

The first thing to do is to figure out the shift mode (S1,S0). In all cases only one shift can work:

0000, 1101, 1110 => shift right
1000, 0001, 0011, 0110 => shift left
1111 => load all zeros

Since not all combinations of Q0-Q3 are used in the sequence, there are many valid functions from Q0-Q3 to S0,S1. I notice that you can make the decision based on the number of 1 bits.

Now that you know how each code shifts, you can calculate the input bit (LSI/RSI)

0000, 1101, 1110 => LSI=1
1000, 0001, 0110 => RSI=1
0011 => RSI=0

Looks like LSI can always be 1.

There are lots of functions that are valid for RSI. RSI=NOT(Q0&Q1) works.