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What are labels used for in VHDL?

A lot of VHDL structures has the option for an optional_label before the declaration, but what is this label used for?

Here is a process declaration example from vdlande showing the option for a label:

optional_label: process (optional sensitivity list)
    -- declarations
begin
    -- sequential statements
end process optional_label;
Solution

  • Labels are used for identification.

    IEEE1076-2008 for instance says

    7.3.1 General

    A configuration specification associates binding information with component labels representing instances of a given component declaration.

    consider the next piece of code:

    entity e is end entity;
architecture a of e is begin
    process is begin wait; end process;
    foo: process is begin wait; end process;
end architecture;

    In simulation (with modelsim) this will show as enter image description here

    I.e. label foo is fixed, while the other process is just assigned some reference, in this case the line number. Is you are using attributes, configurations, aliases, etc, you often need to refer to specific objects and their location. You need fixed names for that.

    If you look at the IEEE1076-2008 standard, you can see that about every statement can have a label: if, case, loop, etc.