RISC-V branch offset machine instruction encoding

Question

What's the decoded RISC-V assembly instruction of: 0001100 01010 11100 100 10001 1100011 ? From the specification i know, that the opcode is the BLT instruction and rs1 = x28, rs2 = x10.

But what is the encoded offset? imm[12|10:5] is 0001100 = 12 and imm[4:1|11] is 10001 = -8, right? Where will the jump go?

Answer 1

.word 0x18ae48e3

blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello
hello:
blt x28,x19,hello
blt x28,x19,hello
blt x28,x19,hello



00000000 <hello-0x38>:
   0:   18ae48e3            blt x28,x10,990 <hello+0x958>
   4:   033e4a63            blt x28,x19,38 <hello>
   8:   033e4863            blt x28,x19,38 <hello>
   c:   033e4663            blt x28,x19,38 <hello>
  10:   033e4463            blt x28,x19,38 <hello>
  14:   033e4263            blt x28,x19,38 <hello>
  18:   033e4063            blt x28,x19,38 <hello>
  1c:   013e4e63            blt x28,x19,38 <hello>
  20:   013e4c63            blt x28,x19,38 <hello>
  24:   013e4a63            blt x28,x19,38 <hello>
  28:   013e4863            blt x28,x19,38 <hello>
  2c:   013e4663            blt x28,x19,38 <hello>
  30:   013e4463            blt x28,x19,38 <hello>
  34:   013e4263            blt x28,x19,38 <hello>

00000038 <hello>:
  38:   013e4063            blt x28,x19,38 <hello>
  3c:   ff3e4ee3            blt x28,x19,38 <hello>
  40:   ff3e4ce3            blt x28,x19,38 <hello>

00000001001111100100001001100011
00000001001111100100000001100011
11111111001111100100111011100011


0 000000 1001111100100 0010 0 1100011
0 000000 1001111100100 0000 0 1100011
1 111111 1001111100100 1110 1 1100011 

you do see how to extract these numbers from the instruction as documented yes?

0 0 000000 0010 0
0 0 000000 0000 0
1 1 111111 1110 0

0 0000 0000 0100 = 0x0004 
0 0000 0000 0000 = 0x0000 (<-- hello label here)
1 1111 1111 1100 = 0x1FFC

Okay so no magic here, sometimes there is an offset, often there is an offset. Often the address of the next instruction is where the immediate is applied. With ARM for example the address of two instructions ahead is where the offset is applied.

from your instruction
0001100 01010 11100 100 10001 1100011
0 001100 01010 11100 100 1000 1 1100011
010011001000 (add implied zero for bit 0)
0 1001 1001 0000 = 0x990