Accessing one variable in a for loop within a VHDL process

Question

I want to increment a variable within a for loop, that indicates me how often a conditional statement is true within a vector. Knowing that for loops in VHDL creates n parallel instances, is it possible that these "access" one variable? Considering following scenario, which works perfectly fine in simulation, I have doubt that it also work in reality. Could someone clarify how it works in reality?

variable_p : process(clk)
 variable var : integer;
begin
  if rising_edge(clk) then
    var := 0;
    for i in 0 to 7 loop
      if some_vector(i) = '1' then
        var := var + 1;
        other_vector(var) <= '1';
      end if;
    end loop;
  end if;

Update

I synthesized following design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity var_p is
  Port (
    clk : in std_logic;
    some_vector : in std_logic_vector( 7 downto 0 );
    other_vector : out std_logic_vector( 7 downto 0 )
  );
end var_p;

architecture Behavioral of var_p is
begin
  var_p : process( clk )
    variable var : integer range 0 to 7;
  begin
    if rising_edge( clk ) then
      var := 0;
      for i in some_vector'range loop
        if some_vector(i) = '1' then
          var := var + 1;
          other_vector(var) <= '1';
        end if;
      end loop;
    end if;
  end process;
end Behavioral;

This results in a LUT for each other_vector element that takes as input several some_vector element [1]. From this I would conclude that indeed var gets 'incremented' for each '1' in some_vector. I now also better understand that a variable is just a helper construct for determining the LUT configuration and nothing that gets synthesized. But please correct me if I am wrong here, because I am still not one hundred percent sure. If I get a board in my hand I will try verify my observations in reality.

[1] https://i.sstatic.net/anrTb.jpg

Answer 1

As I finally found my Basys3 board, I could try out the design. Indeed the synthesized and implemented design works as desired:

The number '1' in other_vector is exact the number of '1' in some_vector.

In my test I connected the input vector to the switches and the output vector to the LEDs (see below).

This confirms that in each 'iteration' of the for loop var is incremented for every element that is '1'.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity var_p is
  Port (
    CLK100MHZ : in std_logic;
    sw : in std_logic_vector( 15 downto 0 );
    LED : out std_logic_vector( 15 downto 0 )
  );
end var_p;

architecture Behavioral of var_p is
begin
  var_p : process( CLK100MHZ )
    variable var : integer range 0 to 15;
  begin
    if rising_edge( CLK100MHZ ) then
      var := 0;
      LED <= ( others => '0' );
      for i in SW'range loop
        if sw( i ) = '1' then
          var := var + 1;
          LED( var ) <= '1';
        end if;
      end loop;
    end if;
  end process;
end Behavioral;