Under Chisel 3, it takes 10 min to compile the Verilator generated C++ of Rocket Chip. Are there any ways to speed this up?

Question

We are modifying Rocket Chip code. After each modification, we need to run the assembly programs, to be sure everything still runs correctly.

To do this, the steps are: 1) Run Chisel, to generate Verilog 2) Run the verilog through Verilator, to generate C++ 3) Compile generated C++ 4) Run tests

Step 3 is about 10 times longer than it was under Chisel 2. It takes about 10 minutes, which slows development.

Is there any way to speed this up?

Answer 1

I have found a non-trivial amount of build and run time is spent on not-really-synthesizable constructs that are used for verification support.

For example, I disable the TLMonitors through the Config options. You can find an example in the subsystem Configs.

class WithoutTLMonitors extends Config ((site, here, up) => {
  case MonitorsEnabled => false
})