Has Vivado unlearned to do type inference?

Question

I have masses of entity instances like that:

GPIO : entity L_PicoBlaze.pb_GPIO_Adapter
  generic map (
    [...]
  )
  port map (
    Clock    => CPU_Clock,   -- Clock : in STD_LOGIC;
    Reset    => '0',         -- Reset : in STD_LOGIC;  -- line 645
    [...]
  );

The code from above is working with:
- ISE XST 14.7
- Quartus II 13.x
- ISE iSim 14.7
I'm also sure, I successfully compiled my design with Vivado 2013.x !!!

Vivado (2014.4) Synth complains, that there are 3 possible type resolutions for '0':
[Synth 8-2396] near character '0' ; 3 visible types match here ["D:/git/.../PicoBlaze/System.vhdl":645]

Reset is declared as following:
Reset : in STD_LOGIC

I can solve this problem by using a qualified expression:

GPIO : entity L_PicoBlaze.pb_GPIO_Adapter
  generic map (
    [...]
  )
  port map (
    Clock    => CPU_Clock,
    Reset    => STD_LOGIC'('0'),  -- line 645
    [...]
  );

I think this (a) looks bad and (b) is a bug in Synth.

I think ISE XST and other tools are doing reverse/backward type inference to determine the correct literal type.

Has anyone encountered this problem, too?
Is my coding style so bad, if I write '0', x"00..00" or "00..00" in port maps?

Edit 1 - Minimal and Complete Example:

library IEEE;
use     IEEE.std_logic_1164.all;

entity top is
  port (
    Clock   : in  STD_LOGIC;
    Reset   : in  STD_LOGIC;
    OUTPUT  : out  STD_LOGIC
  );
end entity;

architecture rtl of top is
begin
  toggle : entity work.TFF
    port map (
      Clock    => Clock,
      Reset    => '0',            -- line 17
      Q        => Output
    );
end;

-- a simple toggle flip flop
library IEEE;
use     IEEE.std_logic_1164.all;

entity TFF is
  port (
    Clock   : in  STD_LOGIC;
    Reset   : in  STD_LOGIC;
    Q       : out  STD_LOGIC
  );
end entity;

architecture rtl of TFF is
  signal Q_r    : STD_LOGIC    := '0';
begin
  process(Clock)
  begin
    if rising_edge(Clock) then
      if (Reset = '1') then
        Q_r    <= '0';
      else
        Q_r    <= not Q_r;
      end if;
    end if;
  end process;
  Q    <= Q_r;
end;

Vivado 2014.4 Error message:
[Synth 8-2396] near character '0' ; 3 visible types match here ["D:/Temp/OverloadTest/overload.vhdl":17]

Edit 2:

I found a working example: I just put the declaration of entity tff in front the top-level declaration. It seams that a [Synth 8-2396] near ..... visible types match here error message from Vivado just a clumsy way to tell us, it can't find a reference to an entire component / file?

I'll need some time to recheck my file list (>300) for missing files/components.

Answer 1

The wrong type overload resolution is caused by an earlier or later syntax error in the same source file.

Look for errors around the instance. Fixing all type overload problems will unveil that it's not related to types, but to another error. When you fix that error, you can revert all fixes for the type overloads and they will now work.