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verilogsystem-verilogmodelsim

System Verilog Bus Routing

In system verilog, I know you can route a partial bus with array[15:8] as a way to split lanes. Is there any way to do this in a non continuous way. For example, lane 2,3,8,9 .

Solution

  • Alternative to Enze Chi way is to use concatenation:

    wire [3:0] a;
assign a = {b[9:8],b[3],b[2]};