Cache request in Forth CPU
In the RAM of the computer a longer program is stored, written in the Forth programming language. It contains of three subfunctions and takes too many bytes for storing them in the first-level-cache of the CPU.
A caching strategy is needed which decides, that only a window of the RAM is copied into the CPU cache. The Forth CPU is able to read from the first-level-cache, but not from the RAM because access to the RAM takes to much time.
In the figure, the instruction pointer is directing to the first word and has executed one command so far and will reach the end of the word “:add” in a short time. But what will happen then?
If the CPU has executed the last command in the first-level-cache (+) there are no further commands. Which part of the Forth CPU decides to unload the current content of the CPU cache and retrieves the new chunk from the RAM?
I'm not sure if this has something to do with “block buffers”, “stack caching in the Forth VM” or “hardware-based CPU cache. The literature is a bit confusing:
Actually, it seems to be a general question not specific to a Forth CPU.
The part of a CPU that retrieves data from memory into the cache is known as cache controller unit or cache control circuitry.
See also: Microprocessor Design/Cache wikibook, How does CPU identify if the instructions are decoded question.
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