VHDL : how to transform a Binary number into a decimal number

Question

I am learning VHDL through a project and I would like to transform a binary number into a decimal number (also expressed in binary). I need to do so because I am printing the number in decimal and if I try to print it without converting it I obtain an hexadecimal number...

For example I have 0010 1010 1111 0001 (2AF1) and I want 0001 0000 1001 1001 0011 (10993)

I must precise that my binary number is on 32 bits

It must be very simple because I can't find the solution on the internet ...

EDIT : This code is working and transform a binary number into a decimal number expressed in binary (d'10 = b'0001 0000)

    signal val0 : std_logic_vector(31 downto 0);
    signal val1 : std_logic_vector(31 downto 0);
    signal val2 : std_logic_vector(31 downto 0);
    signal val_Mux : std_logic_vector(31 downto 0);

            val_MUX <= std_logic_vector(unsigned(val0)+1) when cpt50M_Comp = '1' else val0;


    val1(3 downto 0)<= val_MUX(3 downto 0);
    loopA:
        for i in 0 to 6 generate
            val1(4*i+7 downto 4*i+4) <= std_logic_vector(unsigned(val_MUX(4*i+7 downto 4*i+4))+1) when val1(4*i+3 downto 4*i) > "1001" 
                    else val_MUX(4*i+7 downto 4*i+4);
            val2(4*i+3 downto 4*i) <= "0000" when val1(4*i+3 downto 4*i) > "1001" 
                    else val1(4*i+3 downto 4*i); 

    end generate loopA;
    val2(31 downto 28)<= val1(31 downto 28);


    val0 <= (others => '0') when reset='1' else 
        val2 when rising_edge(clk50);

Answer 1

The solution was to go through 2 others signal before assigning the one display and assign the counter with the one display as done below :

signal val0 : std_logic_vector(31 downto 0);
signal val1 : std_logic_vector(31 downto 0);
signal val2 : std_logic_vector(31 downto 0);
signal val_Mux : std_logic_vector(31 downto 0);

        val_MUX <= std_logic_vector(unsigned(val0)+1) when cpt50M_Comp = '1' else val0;


val1(3 downto 0)<= val_MUX(3 downto 0);
loopA:
    for i in 0 to 6 generate
        val1(4*i+7 downto 4*i+4) <= std_logic_vector(unsigned(val_MUX(4*i+7 downto 4*i+4))+1) when val1(4*i+3 downto 4*i) > "1001" 
                else val_MUX(4*i+7 downto 4*i+4);
        val2(4*i+3 downto 4*i) <= "0000" when val1(4*i+3 downto 4*i) > "1001" 
                else val1(4*i+3 downto 4*i); 

end generate loopA;
val2(31 downto 28)<= val1(31 downto 28);


val0 <= (others => '0') when reset='1' else 
    val2 when rising_edge(clk50);