Why there are different memory sections for RAM in ARM Cortex M3 MCUs?

Question

I am using NXP LPC 1837 which is Cortex M3 based architecture and have bee using its 136k of ram which is divided in sections like belowMemory overview

I don't know why there are different sections of RAM and what is the use of each section?

Answer 1

See the Cortex M3 Memory Map. This describes that the region 0x00000000-0x1FFFFFFF is designated as the 'code' region, and the 0x2....... region is the SRAM region. This (simplistically) allows the core to access both instruction and data faster because the accesses can be routed to independent locations.

Within this, the breakdown is implementation specific. There may be power or performance impacts. For example, from the LPC18xx user guide we can see that there are several bus masters, and a multi-layer AHB which allows independent accesses to different memory blocks without contention.