Expecting type void, Syntax error near "process" with transport delay code - vhdl error transport

Question

I'm new to FPGA and I'm trying to code a simple demo with transport delay. but I got the following errors:

1.ERROR:HDLCompiler:806 - "../PGAND2.vhd" Line 54: Syntax error near "process".
2.ERROR:HDLCompiler:841 - "../PGAND2.vhd" Line 55: Expecting type  void for <behavioral>.

I'm confused about this and I can't solve this. Could you please give me some tips to solve this, thanks a lot! Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PGAND2 is
    generic( trise : TIME := 1ns ;
            tfall : TIME := 1ns ) ;
    port(   a0 : in std_logic ;
        a1 : in std_logic ;
        z0 : out std_logic ) ;
end PGAND2;

architecture Behavioral of PGAND2 is

begin
process ( a1, a0) 
    variable zdf :std_logic ;
    begin 
        zdf := a1 AND a0 ;
        if zdf = '1' then
            z0 <= transport zdf after trise ;
        else if zdf = '0' then
            z0 <= transport zdf after tfall ;
        else
            z0 <= transport zdf ;
    end if ;
    end process ;
end Behavioral;

The environment is ISE 14.7 on Windows 10. Thanks a lot!

Answer 1

The if then else statement format in VHDL like below:

if [condition] then 
   [statements]
else 
   [statements]
end if;

And then else if statement is not elsif so else if statement itself needs end if keyword.

You should use elsif keyword or else if ... then ... end if statement.

The correct code for your description is :

process( a1, a0) 
    variable zdf :std_logic ;
begin 
    zdf := a1 AND a0 ;
    if zdf = '1' then
        z0 <= transport zdf after trise ;
    elsif zdf = '0' then
        z0 <= transport zdf after tfall ;
    else
        z0 <= transport zdf ;
    end if ;
end process ;

Or

process( a1, a0) 
    variable zdf :std_logic ;
begin 
    zdf := a1 AND a0 ;
    if zdf = '1' then
        z0 <= transport zdf after trise ;
    else if zdf = '0' then
        z0 <= transport zdf after tfall ;
        end if;
    else
        z0 <= transport zdf ;
    end if ;
end process ;