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mipscomputer-sciencecpu-architecturecpu-cache

MIPS 2-Way Cache


I've got a cache for a MIPS 64 bit architecture, 2-way of 4KB per block and lines of 16 words (for every block). I have to determine:

  1. [ TAG | Index | Offset ]

    Bit sizes for every field

  2. How many bit is the entire memory made of?


I've got no clue if what I've done is correct since I don't have the results, since we are working with 64bit MIPS and not 32 I thought that a word would have been made out of 8 bytes instead of 4.

I've calculated the numbers of blocks by doing 4KB / (16 words * 8 byte) = 32

Then I've done 32 / 2-way= 16 --> 4 bit of INDEX

Then I got word and byte offset as follows:

16 words --> 4 bit word offset

8 byte --> 3 bit byte offset

Finally I calculated the TAG as 64 - 4(index) - 4(word offset) - 3 (byte offset) = 53 bit

And the total number of bit would have been 53 tag + 64 + 1 validate = 118 which multiplied by the number of blocks(32) would have given 3776 bit.

I'm not completely sure about the result, can someone help me with this?

Thanks.


Solution

  • Part of the question is not very clear, I'll try to make a best guess.

    Assumption : Cache size is 4KB, word is 64 bits, memory is byte addressing.

    Information : Cache line is 16 words wide, and its a 2-way set assoc cache.

    Cacheline size = 16 word * 64 bits (8 byte) = 128 byte
    Number of cachelines = 4 KB/128 B = 32
    Number of blocks = 32 / 2 (2-way) = 16
    As the memory is byte addressable, least 3 bits of the address can be ignored.
    Next 4 bytes will be used to offset in a word in the 16 word cacheline.
    Next bit of the address is ignored because its 2-way assoc
    As there are 16 blocks, next 4 bits will be used to index a block.
    That leaves 64 - (4 + 1 + 4 + 3) = 52 bits for the TAG.
    
    TAG - 52 bits [bits 12 to 63]
    Index - 4 bits [bits 8 to 11]
    Offset - 4 bits [bits 3 to 6]
    

    Its bit hard to answer to the second question as a cache would typically have extra bits per cacheline, like valid bits etc. For the sake of simplicity lets assume this cache only has a TAG per cacheline. This gives us 52 bits * 16 blocks * 2 lines in a block = 1664 bits = 208 bytes.

    Therefore the whole cache size would be

    = 4 KB + 208 B
    = 4096 B + 208 B
    = 4304 Bytes