Consider a processor XYZ with address bus and 24-bit data bus. XYZ provides support for virtual memory and demand paging. For logical to physical address translation, the first 12 most significant address bits corresponds to the page number and the last 12-bits are used as offset.
a) What is the maximum number of physical memory pages that can be supported by XYZ? b)And what is the size of a memory page in bytes?
The solution is given as:
a)2^12 number of pages
b)2^12 bytes
I understood part (a) but I just can't figure out how was the size of the memory page calculated with the given info. I think it has to do something with the offset but I'm not sure.
The offset is used to 'seek' within the page so you can't make pages bigger than the seek range