Do input and output ports behave like flip-flops? (VHDL)

Do input and output ports in VHDL behave like flip-flops, i.e. are they updated on a rising or falling edge of a clock? Here is an example of what I mean.

entity main is
    port(
        clk : in std_logic; -- FPGA clock
        x : in std_logic; -- input signal
        y : out std_logic -- sampled input signal
    );
end entity main;

architecture RTL of main is
    signal y_q : std_logic;
begin

    y <= y_q; -- set the output

    copy : process(clk, x) is
        variable y_d : std_logic;
    begin
        y_d := x; -- continuously sample x
        if rising_edge(clk) then -- synchronous logic
            y_q <= y_d; -- update flip-flop
        end if;
    end process copy;

end architecture RTL;

The program above simply samples the input signal x, and sends it to the output y. The signal y_q is the sampled input signal x, whereas a sample is taken on every rising edge of a clock clk. However, I'm confused about the y signal - is that signal completely the same as y_q, or it is delayed by one clock cycle?

Solution

y <= y_q just "wires up" y to y_q. There's no extra logic implied, so there's no delay.

Alternatively, you can just look at the RTL generated for this module! The screenshot below is from Xilinx ISE. ("fd" is the Xilinx name for a D-type flip-flop.)