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freertoscortex-m

Why is an ISB needed after WFI in Cortex-M FreeRTOS?

I see the following lines in the Cortex-M port of FreeRTOS when using the tickless idle functionality that relies on the WFI instruction

__asm volatile( "dsb" );
__asm volatile( "wfi" );
__asm volatile( "isb" );

See https://github.com/cjlano/freertos/blob/V9.0.0/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c#L530

I see that per the ARM Cortex-M Programming Guide to Memory Barrier Instructions document: "A DSB should be used to ensure that there are no outstanding memory transactions prior to executing the WFI or WFE instruction."

But I am curious about why the ISB is necessary here? Perhaps this ensures that the interrupt which awoke the chip from WFI executes immediately before any further instructions that might be sitting in the pipeline? That's my best guess but would like to hear any other thoughts or confirmation.

Solution

  • I believe the intention of the ISB is to ensure that the wfi instruction is executed "in order" and no instructions after it are executed until it wakes up. That said, I do not think that it is required according the the ARM documentation. I suspect it is belt and braces approach.