There are several cache coherence protocols around there, such as MSI, MESI, MOSI, MOESI, etc.
Let's suppose this scenario: A CPU contains 4-cores with L1 private cache (L1 cache size does not matter here). The memory addresses here are illustrative.
Core-0 requests a memory access to address 0x1111, thus the value will be loaded into its L1 cache line from the main memory.
Core-1 requests a memory access to address 0x2222, thus the value will be loaded into its L1 cache line from the main memory.
Core-2 requests a memory access to address 0x1111 (previously accessed by Core-0). This reference is already loaded into Core-0's cache line, thus, the cache coherence protocol will copy the Core-0's cache line that contains the reference and finally store it into Core-2's cache line.
Question 1: Does core-2 knows that the memory access has been served by Core-0's cache line instead of main memory? Or the Cache Coherence Protocol is transparent to where the data has been retrieved?
Question 2: Core-0, and Core-2 have their cache line in Shared state after step 3. However, is possible to Core-2 gets the currently state from a given memory reference from a different core? In this case, is possible Core-2 knows that for this memory reference 0x1111 Core-0 cache line is in Shared state?
Does core-2 knows that the memory access has been served by Core-0's cache line instead of main memory?
Yes, in the described scenario the cache line should be in "shared" state (i.e. the cache line is shared between few cores). But please see below...
The Cache Coherence Protocol is transparent to where the data has been retrieved?
Yes, the cache coherence protocol is transparent for the core and the cache line states are internal. Some architectures might have instructions for direct cache state access, but I doubt so. Most of architectures have just prefetch/zero/flush/invalidate instructions...
So the answer for the next questions is obvious:
Core-0, and Core-2 have their cache line in Shared state after step 3. However, is possible to Core-2 gets the currently state from a given memory reference from a different core?
It might be possible on some architectures, but it is rather not possible on x86.
In this case, is possible Core-2 knows that for this memory reference 0x1111 Core-0 cache line is in Shared state?
Same as above. Cache is coherent, so the instruction level interface to the cache is very simple on most architectures.
Overall, it looks like XY Problem. What are you trying to achieve with the cache-line-state-aware cores?