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cperformancecachingcpu-cache

How data structures cache aligned are invalidated in L1 cache line

I am trying to understand the L1 cache mechanism of CPUs.

  1. Let's suppose the CPU has 4 cores and the L1 cache line size is 64 bytes with N entries for each core using MESI protocol.

  2. Thus a memory reference is loaded aligned with the cache line size (the reference is some kind of data structure that holds 64 bytes exactly).

  3. At this time, the Core-0 modifies 4 bytes (at offset 0) in this cache line.

  4. Then, Core-1 references the same memory location. Thus, the Cache Coherence Protocol identifies this operation and copy the cache line in Core-0 to the Core-1 (avoiding reading from main memory).

  5. Core-1 thus modify 4 bytes (at offset 15) in this cache line.

My question is this: the Cache Coherence Protocol will invalidate the cache line in Core-0 or not? Although the modification are in different offsets.

Also, at this point, could someone tell what is the Cache Coherence Protocol (MESI) state for this cache line reference?

Solution

  • The MESI protocol operates on cache lines so the offsets within a single cache line does not matter.

    When core-1 initially requests for the cache line from core-0, it is copied over and the state for both cores is set to S (shared). When core-1 modifies the cache line, the cache line in core-1 is set to M (modified) while for core-0 it is set to I (invalid).