Testbench of SR Fliflop in VHDL

Question

I wanted to implement an SR flipflop using VHDL. I wrote the code for the flipflop as well as the testbench. But the testbench doesn't compile correctly and gives errors which I can't figure out. I am using ghdl to compile. Please help.

This is the code for the flipflop.

library ieee;
use ieee.std_logic_1164.all;

entity sr_flipflop is
    port 
    (
        s,r,clock: in std_logic;
        q,qbar: inout std_logic
    );  
end sr_flipflop;

architecture arc of sr_flipflop is
    signal x,y: std_logic;
begin
    process (clock,s,r) begin
        x<=r and clock;
        y<=s and clock;
        q<=qbar nor x after 10 ns;
        qbar<=q nor y after 10 ns;
    end process;
    process (x,y) begin
        q<=qbar nor x after 5 ns;
        qbar<=q nor y after 5 ns;
    end process;
end architecture arc;

This is the code for the testbench.

library ieee;
use ieee.std_logic_1164.all;

entity sr_flipflop_tb is
end entity sr_flipflop_tb;

architecture arc of sr_flipflop is
    component sr_flipflop is
        port 
        (
            s,r,clock: in std_logic;
            q,qbar: inout std_logic
        );  
    end component sr_flipflop;

    signal clock:std_logic:='0';
    signal s,r:std_logic;
    signal q:std_logic:='0';
    signal qbar:std_logic:='1';
    constant half_period:time:=30 ns; 

begin
    port_map:sr_flipflop port map(clock=>clock,s=>s,r=>r,q=>q,qbar=>qbar);

    process begin
        clock <= not clock after half_period;
    end process;
    process begin
        s<='0';
        r<='0';

        s<='0' after 40 ns;
        r<='1' after 40 ns;

        s<='1' after 80 ns;
        r<='0' after 80 ns;

        s<='1' after 120 ns;
        r<='1' after 120 ns;
    end process;

end architecture arc;

The first file compiles without error, but when I give the following command at the cmd,

ghdl -a sr_flipflop_tb.vhd

I get the following errors:

sr_flipflop_tb.vhd:16:15: identifier 'clock' already used for a declaration
sr_flipflop.vhd:7:20: previous declaration: port "clock"
sr_flipflop_tb.vhd:17:15: identifier 's' already used for a declaration
sr_flipflop.vhd:7:16: previous declaration: port "s"
sr_flipflop_tb.vhd:17:17: identifier 'r' already used for a declaration
sr_flipflop.vhd:7:18: previous declaration: port "r"
sr_flipflop_tb.vhd:18:15: identifier 'q' already used for a declaration
sr_flipflop.vhd:8:16: previous declaration: port "q"
sr_flipflop_tb.vhd:19:15: identifier 'qbar' already used for a declaration
sr_flipflop.vhd:8:18: previous declaration: port "qbar"
sr_flipflop_tb.vhd:26:16: port "clock" can't be assigned
sr_flipflop_tb.vhd:29:16: port "s" can't be assigned
sr_flipflop_tb.vhd:30:16: port "r" can't be assigned
sr_flipflop_tb.vhd:32:16: port "s" can't be assigned
sr_flipflop_tb.vhd:33:16: port "r" can't be assigned
sr_flipflop_tb.vhd:35:16: port "s" can't be assigned
sr_flipflop_tb.vhd:36:16: port "r" can't be assigned
sr_flipflop_tb.vhd:38:16: port "s" can't be assigned
sr_flipflop_tb.vhd:39:16: port "r" can't be assigned

Please shed some light. Thanks.

Answer 1

Line 7 in your testbench is

architecture arc of sr_flipflop is

This seems to be a copy&paste error, it should be

 architecture arc of sr_flipflop_tb is

This should cause these error messages.

Note that your code, in and of itself, is not exactly ideal. In Modelsim your testbench would not run at all(I don't know about GHDL). Maybe check out this tutorial. It's slightly dated, but it works.