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vhdlresettest-bench

How to manage reset signal for VHDL testbenches?

I have a very simple VHDL testbench that should run.

My components all have a reset signal, so that registers are set to 0 and other components correctly initialized, but if I create a common signal for resetting all component only during the first clock cycle, how can I tell to that signal to go down after the first clock cycle and never get up again?

Solution 
  • reset <= '1', '0' after 10 ns;