I have multiple inputs that belong together(get sampled at the same clock etc.) but are not logically a vector(i.e. not a parallel bus) in a piece of existing code I need to modify.
Previously, they were defined as
type my_type is array (my_width - 1 downto 0) of std_logic;
signal my_signal : my_type;
Until now, for this purpose, I always used this:
subtype my_subtype is std_logic_vector(my_width - 1 downto 0);
signal my_signal : my_subtype;
For most intentions and purposes, an array and a vector can be handled pretty much the same, so my question is:
Is there any advantage to either way of doing things? Is there a preferred/standard way?
There is a difference, which has to do with strong typing.
With your first piece of code, you create a new type. It is independent and not compatible with other types. Just consider the next piece of code:
entity e is end entity;
library ieee;
architecture a of e is
use ieee.std_logic_1164.all;
type slv1_t is array (15 downto 0) of std_logic;
signal slv1 : slv1_t;
type slv2_t is array (7 downto 0) of std_logic;
signal slv2 : slv2_t;
begin
slv2 <= slv1(7 downto 0);
end architecture;
When compiling in modelsim, this code will give errors:
Error: C:/HDL/TypeVsSubtype/Type.vhd(10): Cannot resolve slice name as type slv2_t.
For the second piece of code, the underlying type is still a std_logic_vector. Thus the subtypes are compatible. Consider the next piece of code:
entity e is end entity;
library ieee;
architecture a of e is
use ieee.std_logic_1164.all;
subtype slv1_t is std_logic_vector(15 downto 0);
signal slv1 : slv1_t;
subtype slv2_t is std_logic_vector(7 downto 0);
signal slv2 : slv2_t;
begin
slv2 <= slv1(7 downto 0);
end architecture;
This does compile (i.e. no errors).