How to synchronize two unrelated UVM sequence items from different UVM agents?
This is my scenario for verifying a Parity Encoder-Decoder DUT. Decoder Input agent here is the re-active agent and injects error into the data stream captured from Passive monitor in Encoder Output agent.
Now I have sequence and sequence items separately for both encoder and decoder input agents. But how do I synchronize both the agents such that decoder re-active agent adds error and creates a new packet for every data in order.
e.g suppose encoder sends data in the order - 1000, 1010, 0100, 1011 and decoder re-active agent creates error packets in the order (one hot bit) - 0010, 1000, 0001, 0100. Now both create data packets unrelated to each other. However the re-active agent should xor 1st data with its 1st packet like 1000 ^ 0010 even if it receives two data i.e 1000 and 1010 together from the passive agent monitor. Also since both agents are generating items, decoder should not send an item before it receives data from encoder agent (via passive encoder agent monitor).
I think, you want to use the lockign mechanism between different objects.
You can use the IPC (Interprocess Communication) methods to control that, like events, mailboxes, semaphores.
In UVM, the advanced methods are available, like uvm_event, TLM FIFOs, which can be used in your purpose.
- Output not updated as expected
- Static vs. automatic tasks
- Why do I get a syntax error using the ternary operator with function calls?
- Constraint to randomize such a way that consecutive 2 bits are set to 1, other bits are 0 for 16-bit variable
- Verilog port mapping when a gate netlist module's vector ports instatantiated inside an rtl module have been split into each bit by P&R tool
- How to declare virtual interface with params in the top module (in the testbench)?
- One IMP_PORT connected to multiple EXPORTS
- Classes method execution and systemverilog regions
- Systemverilog/Verilog VCP2000 “Syntax error. Unexpected token: class[_IDENTIFIER].”
- Use loop to access generated modules
- How to check signal drive strength?
- Array of wire OR-reduction is wrong
- SystemVerilog constraint for mapping between two 2D arrays
- Random constraints on array of structure elements
- $dumpfile and $dumpvars not working in vscode. Error in terminal says requires SystemVerilog
- import constant dpi-c function in systemverilog
- How to implement Summation equation in SystemVerilog constraints?
- What's the best way to tell if a bus contains a single x in Verilog?
- Reducing OR not working as expected when bit slicing in a loop
- Why does "assign a = a/2" (inside a task) only cause a single value change?
- stream operands require explicit typecast to be used as argument of system task/function
- SystemVerilog testbench: Making an array of logic with run-time determined width
- Why does blocking vs. non-blocking matter in this Verilog snippet?
- How can I schedule multiple inputs into an instantiated SystemVerilog module?
- How can I declare an output of a module to be a decimal number instead of a single bit?
- T flip-flop using dataflow model
- System Verilog: Biitwise coverage for multibit signal
- Use if-generate structure to define two variations of a function, and call that function in the same tb
- SystemVerilog inheritance, aggregated classes and parent function call
- String triple quotes not getting accepted by simulators