This design contains one or more registers/latches that are directly incompatible with the Spartan6 architecture

Question

I'm new in this world.

Actually, I'm learning VHDL. I've written the below code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Problems is
    port(
        S   : in std_logic;
        D   : in std_logic;
        CLK : in std_logic;
        R   : in std_logic;
        Q   : out std_logic;
        Q_n : out std_logic
    );
end Problems;

architecture Behavioral of Problems is
    signal t_tmp1 : std_logic; 
begin
    DFF: process (S,R,D,CLK)
    begin
        if (S = '0' and R = '0') then
            t_tmp1 <= not t_tmp1;
        elsif (S = '0' and R = '1') then
            t_tmp1 <= '1';
        elsif (S = '1' and R = '0') then
            t_tmp1 <= '0';
        elsif (rising_edge(CLK)) then
            t_tmp1 <= D;

        end if;
    end process DFF;
    Q    <=  t_tmp1;
    Q_n <= not t_tmp1;

end Behavioral;

When I synthesized appear me the below warnings:

WARNING:HDLCompiler:92 - "/home/joseph/ISEProjects/Exercise_BasicMemoryElements/Problems.vhd" Line 41: t_tmp1 should be on the sensitivity list of the process

WARNING:Xst:3002 - This design contains one or more registers/latches that are directly incompatible with the Spartan6 architecture. The two primary causes of this is either a register or latch described with both an asynchronous set and asynchronous reset or a register or latch described with an asynchronous set or reset which however has an initialization value of the opposite polarity (i.e. asynchronous reset with an initialization value of 1).

The simulation works well.

I want to know why the warnings and what do I have to learn to solve problems like this.

Regards,

Joseph Peña.

Answer 1

If you were to read through Spartan-6 Libraries Guide for Schematic Designs you'd find a D flip flop with both an asynchronous Preset and asynchronous Clear isn't provided by Spartan 6 (or later device families for that matter).

Your if statement's first condition statement's behavior doesn't appear to represent what would happen if both a reset and a set were TRUE at the same time either. A distinction between what you can simulate and what you can technology map through synthesize.

In Spartan-3e for instance the reset would override the set:

Constraints on the synthesis eligible subset of the VHDL language for mapping into Register Transfer Logic elements in a target technology are found in IEEE Std 1076.6-2004, now rescinded, and can be found for Xilinx either in the ISE XST User Guide or Vivado Design Suite User Guide Synthesis (ug901).

The ability to map a VHDL description is predicated on having a supported target for the device family.