SystemVerilog register design race avoidance

Question

While doing digital design in systemverilog, I ran into an issue regarding racing conditions.

The test-bench (which I cannot modify) that drives my design, drives the inputs in such a way that certain registers in the design do not function properly due to a race condition.

Here is an eda-playground example which illustrates what is happening (input changes "before" the clock does, at time 15ns):

http://www.edaplayground.com/x/rWJ

Is there a way to make the design (a simple register in this case) resistant to this particular problem? What I need is a statement like "out_data <= preponed(in_data);" or something similar which will make the order of input signal changes irrelevant.

I have read about #1step in the SystemVerilog LRM but I am unsure how to use it, nor if it can help me with this particular problem at all.

Answer 1

Your test bench is essentially creating stimulus that is in a setup violation to your register. You have two options:

1. Convince the testbench writer of their erroneous ways and get them to fix it.
2. Insert a layer of hierarchy around the design that delays the clock to eliminate the race.