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system-verilogsequencesuvm

How to attach an UVM sequence with a particular sequencer?


I have 3 sequences, and 4 sequencers.

I want

  1. sequencer 1 to run sequence1,
  2. sequencer 2 to run sequence1,
  3. sequencer 3 to run sequence2, sequence3 in serial order.
  4. sequencer 4 to run sequence1, sequence2 in serial order.

One method to do so is inside the test class

task run_phase(uvm_phase phase);
fork
   sequence1.start(sequencer1);
   sequence1.start(sequencer2);
   begin
     sequence2.start(sequencer3);
     //wait for request....
     sequence3.start(sequencer3);
   end
   begin
     sequence2.start(sequencer4);
     //wait for req....
     sequence1.start(sequencer4);
   end
join
endtask

How can I do the same inside each of the sequencers, than doing inside test?


Solution

  • What you have written is the best method of doing what you want (after raising an objection before the fork and dropping it after the join). All other methods make it difficult to add additional sequences before the fork or after the join.

    You can use the uvm_config_db to set the "default_sequence" of each sequencer, but you will need to create another sequence layer for sequencer3 and 4 that starts sequence1 and 2 in the desired order. You will also need to deal with raising/lowering objections inside each default sequence.

    Another option is instead of using generic sequencers, you can define a sequencer and override the run_phase to start each sequence or series of sequences.