VHDL Generate Array Of STD_LOGIC_VECTORS with Reducing Length

Question

I am trying to create an array of std_logic_vectors with reducing lengths. I have tried making an array with a generic std_logic_vector and then using a generate statement to make the vectors.

architecture behavioral of dadda_mul_32bit is

type and_planes is array (0 to 31) of std_logic_vector;    

begin

generate_and_plane:
    for i in 0 to 31 generate
        and_planes(i) <= and_vector(a, b(i), i); 
    end generate generate_and_plane;

end behavioral;

along with a function that returns a generic std_logic_vector:

   function and_vector(vec: std_logic_vector; x: std_logic; length: natural) return std_logic_vector is
    variable result: std_logic_vector(length - 1 downto 0);
begin
    for i in 0 to length - 1 loop
        result(i) := vec(i) and x;
    end loop;

    return result;
end function;

Am I using the generate statement incorrectly?

Answer 1

and_planes is a type not a signal, so you can't assign to it! More over you are creating a partially constrained type, which needs to be constrained in a object (e.g. signal) declaration.

VHDL doesn't support ragged arrays. (Arrays wherein each element is of different size). If you need this for simulation, you can use access types and emulate ragged arrays like in C. If you need it for synthesis, then you can emulate a ragged array with a one-dimensional array and some functions to compute the bounds of a nested vector.

See this answer of me:

• VHDL Multidimensional arrays with different internal size
• vhdl port declaration with different sizes

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Btw. VHDL-2008 adds an overload: "and"(std_logic, std_logic_vector), so no function is needed to calculate the anding of a single bit with each bit in a vector.

-- slice 'a' and gate it by 'b(i)'
and_planes(i) <= a(i downto 0) and b(i);