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system-veriloghdl

What is a difference between following two logic implementation from Hardware perspective?


Implementation 1:

logic [2:0][3:0] reg0; // Packed
always_ff@(clk_a)
   reg0[1:0] <= in0[1:0];
always_ff@clk_b)
   reg0[3:2] <= in1[1:0];

Implementation 2:

logic [2:0] reg0 [3:0]; // unpacked
always_ff@(clk_a)
   reg0[1:0] <= in0[1:0];
always_ff@clk_b)
   reg0[3:2] <= in1[1:0];

Why tool gives me multi-driver error for implementation 1?


Solution

  • The difference is what the LRM considers a variable. You are not allowed to have multiple assignments to the same variable from different processes. A packed array is considered a variable as well as each element if an unpacked array. The reason for this restriction has more do do with efficient simulation implementation and not really with hardware implementation and the distinction about what constitutes a variable is used in other places in the LRM (i.e. pass by reference).