Say there is a B Module in which A is a instance.
class B extends Module {
…
val u_A = Module(new A)
// the way to hook u_A’s port is the issue
}
The description of A Module:
class A extends Module {
val io = IO(new Bundle{
val a = Output(Bool())
})
io.a := true.B
}
The declaration of A BlackBox:
class A extends BlackBox {
val io = IO(new Bundle{
val io_a = Output(Bool()) // HAVE to define port name with io_* prefix otherwise ...
})
}
You MUST define the port name in BlackBox with prefix of io_ otherwise the generated port list in B RTL won’t match to the A Module.
for the Module instantiation, the way to hook u_A’s port is
u_A.io.a
for the BlackBox instantiation, the way to hook u_A’s port is
u_A.io.io_a
Could you enlight me about whether there is a more convinience way?
The mismatch between BlackBox and Module io emission is a legacy API for better integration with Verilog IP where the Chisel designer has little to no control over the Verilog. We are thinking about a more explicit and structured way to handle such "invisible" bundles that drop their prefix since there are other cases where they would be useful.
To answer your question though, there is a more convenient way. We are experimenting with what we call "multi IO modules" where you can use IO(...) multiple times inside of a Module to create ports. You don't actually need that feature here, but it gives us chisel3.experimental.ExtModule--an alternative to BlackBox. ExtModule does not silently drop the prefix so if you switch to extending it instead of BlackBox you will get the desired behavior.