Can I avoid opt_merge from removing a BUF? (Yosys tri-state workaround)

Question

I know yosys has limited tri-state support, but I'm looking for a possible workaround. The following circuit:

module TBUF2
(
inout SALIDA1,
inout SALIDA2,
input OE,
output C);

assign SALIDA1=OE ? 1'b0 : 1'bZ;
assign SALIDA2=OE ? 1'b0 : 1'bZ;

wire e;
assign e=SALIDA1 & SALIDA2;
assign C=e;
endmodule

Is interpreted as:

TBUF2 parsed tree

Note that when OE is 0 C=SALIDA1 and SALIDA2. During the opt pass, the opt_merge pass removes $2 mux and generates:

TBUF2 optimized

This breaks the circuit (when OE is 0 then C=SALIDA1). I realize this is because yosys/ABC doesn't really understand the consequences of the "1'z" input. Is it possible to keep muxes that meet the following criteria?:

1) At least one input is 1'Z

2) Its output drives an inout pin

Here is the script to reproduce it:

read_verilog tbuf2.v
proc
show -format dot -prefix tbuf2_01
opt
show -format dot -prefix tbuf2_02

Answer 1

Convert the tristate buffer $mux cells to $tribuf cells by running the tribuf command after proc and before running any opt commands.