Function clogb2() generated by vivado can't synthesize with loop limit error

Question

I'm trying to design an AXI_master peripheral with vivado. I used the axi peripheral generator in vivado menu and modified the vhdl code generated.

In vhdl code there is a function clogb2 declared with following code:

function clogb2 (bit_depth : integer) return integer is
    variable depth  : integer := bit_depth;
    variable count  : integer := 1;
begin
  for clogb2 in 1 to bit_depth loop  -- Works for up to 32 bit integers
    if (bit_depth <= 2) then
      count := 1;
    else
      if(depth <= 1) then
          count := count;
        else
          depth := depth / 2;
        count := count + 1;
        end if;
    end if;
  end loop;
  return(count);
end;

This works in simulation (GHDL) but fail in synthesis with error :

[Synth 8-403] loop limit (65538) exceeded

I tried to increase loop limit in vivado with following tcl command :

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter max_loop_limit <X>"

As explained here, but vivado synthesize with an infinite time and never finish. Do you know how to solve this problem ?

Answer 1

You could also try a different path. Although floating point is not supported in logic (although support is increasing), it is allowed for internal calculations and such. (By at least Xilinx and Altera/Intel).

Try this:

use ieee.math_real.all;

function ceillog2(input : positive) return natural is
begin
    return integer(ceil(log2(real(input))));
end function;