VHDL fsm error - near "when": (vcom-1576) expecting END

Question

I am trying to make a fsm in vhdl using modelsim but when i try and compile my code i have this errors

** Error: C:/Users/manor/Desktop/ldh/mult_fsm.vhd(34): near "when": (vcom-1576) expecting END.

** Error: C:/Users/manor/Desktop/ldh/mult_fsm.vhd(60): near "when": (vcom-1576) expecting END.

** Error: C:/Users/manor/Desktop/ldh/mult_fsm.vhd(72): near "else": (vcom-1576) expecting END.

And this is my code

library ieee;
use ieee.std_logic_1164.all;

entity mult_fsm is
    port(ck,adx,m: in std_logic;
        adsh,sh,cm,mdone: out std_logic);
end entity mult_fsm;

architecture ideal of mult_fsm is
    type StateType is (S0, S1, S2, S3, S4);
    signal CurrentState, NextState: StateType;
begin
    NS_CS: process( ck)
    begin
    if ck'event and ck='1' then
        case CurrentState is
            when S0=>
            if (adx='0') then
                NextState <= S0;
            else
                NextState <= S1;
            end if;

            when S1=>
                NextState <= S2;

            when S2=>
            if (m='1') then
                NextState<=S3;
            else if (m='0') then
                NextState<=S2;
            end if;
            
            when S3=>
                NextState <= S4;

            when S4=>
                NextState <= S0;

        end case;
    end if;
    end process NS_CS;

    OL: process (CurrentState)
    begin
        case CurrentState is
            when S0=>
            if (adx = '0') then
                adsh<='0';
                sh<='0';
                cm<='0';
                mdone<='0';
            else if (adx = '1') then
                if (m='1') then
                    adsh<='1';
                else if (m='0') then
                    sh<='1';
                end if;
            end if;
            when S1=>
            if (m='1') then
                adsh<='1';
            else if (m='0') then
                sh<='1';
            end if;
            when S2=>
            if (m='0') then
                adsh<='0';
                sh<='0';
                cm<='0';
                mdone<='0';
            else if (m='1') then
                adsh<='1';
            end if;
            when S3=>
            if (m='0') then
                sh='1';
            else if (m='1') then
                cm<='1';
                adsh<='1';
            end if;
            when S4=>
                mdone<='1';
        end case;

    end process OL;

end architecture ideal;

I tried fixing the code myself but i just can't figure out what is the problem with it.

Answer 1

Looking at the following code:

    if (m='1') then
      NextState<=S3;
    else if (m='0') then
      NextState<=S2;
    end if;

I think you meant elsif instead of else if. Alternatively, since m is an std_logic, you may be able to simplify this block down to:

    if (m='1') then
      NextState<=S3;
    else
      NextState<=S2;
    end if;