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verilogxilinxsynthesis

What exactly is the difference between the Xilinx warnings XST:1710 and XST:1895?

Can anyone please explain the difference between the two Xilinx warnings:

Xst:1710 - FF/Latch reg_0 (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

Xst:1895 - Due to other FF/Latch trimming, FF/Latch reg_1 (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

Assuming "reg" is a byte long register.

Solution

  • reg_0 is optimized out (aka trimmed) because it is never assigned but is referenced during the assignment of other registers or nets. Since it does not has a specified init value the synthesizer is defaulting to zero. Therefore the synthesizer can save flop(s) and any use of reg_0 in the design will be treated as logic 0.

    reg_1 is optimized out because its value is depended on other flops that were already optimized out. Using the example below: reg_1 is depended on reg_0. Since reg_0 will always be zero (because it is never assigned), reg_1 will also always be zero. Hence why it says "Due to other FF/Latch trimming". The synthesizer saves flop(s) and any use of reg_1 in the design will be treated as logic 0.

    reg [7:0] reg_0;
reg [7:0] reg_1;
always @(posedge clk) begin
  reg_1 <= in & reg_0;
end

    In summary:

    • Xst:1710 - trimmed because never assigned
    • Xst:1895 - trimmed because depended logic was trimmed

    Same outcome but for different reasons.
    If there is a bug in the design, resolving Xst:1710 issues it could automatically resolve the Xst:1895. If there isn't a bug, then these warnings point to dead code.