Will a VHDL compiler optimise this away or not?

Question

If I have an operation like the one below that depends on a constant parameter will the compiler see that this if statement will always be the first case and therefore optimise it away or not?

entity Thing is 
  generic(
    constant N : integer := 32;
    constant M : integer := 24
);

...

architecture behaviour of Thing is

...

  process(clk)
  begin
    if(rising_edge(clk)) then

      ...

      if N > M then
        -- do a thing
      else
        -- do a different thing
      end if;

    ...
    end if;
  end process;
end behaviour;

Answer 1

In any synthesis tool that I have used, any constants (including generics) get propagated through the design in order to produce the simplest possible output. This is good for performance in general.