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VHDL process style

I have been reading through various questions on here, as I am learning VHDL and always looking to improve. However, this comment made me curious:

Simple State Machine Problem

I was told, in my brief VHDL course at university, that separate processes was best form, to separate the synchronous aspects.

Obviously this is personal preference, but I was hoping that some more experienced users may be able to shed some light on the pros/cons, with their own preferences? Is one more common than the other?

Thanks!

Solution

  • Well, as it was me that said what you've linked to... I'd better comment :)

    Bad things (IMHO) if you put things in separate processes:

    • you have to keep your sensitivity list religiously up to date
    • You have to provide defaults for every output, unless you want asynchronous latches (which you usually don't)
    • The logic is split up, so if you add a state to a state machine, you have to put the new state in both processes
    • If you want a signal to be used both registered and unregistered, you end up duplicated it. With a single process you can use variables to achieve this.
    • some people think it's harder to read.

    Good things:

    • You can have the "output" of a state unregistered. This can be good for reducing latency, but for almost all purposes you want registers on the output of each block to make meeting timing easier.
    • Some people think it's easier to read

    My opinion is that edicts like you heard ("keep it separate") stem from the days when synthesisers weren't very good at differentiating the logic from the flops, so putting just the flops in clocked processes made sense.

    Furthermore, that approach matched the way people of that era drew schematic diagrams before they had HDLs.

    These days, synthesisers can deal with arbitrarily complex logic in clocked processes. And I can write it the way that makes sense without having to be explicit about where each tiny bit of logic sits. Only when timing is really tight do I have to think really hard about placing flops and logic in just the right places.

    My "rules" are:

    • Keep it readable
    • If it meets the requirements (eg power, timing and functions OK), you're done.
    • If not, then and only then play unreadable tricks

    A lot like writing software :)