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system-veriloguvmsystem-verilog-assertions

What would be the best method to check frequencies of clocks that has a +/- tolerance %?


Below is the property that I currently use.

property freq_chk (time clk_period , bit disable_chk=0);
  time current_time; 
  disable iff ( disable_chk )
  ('1, current_time = $time) |=> 
   ( (($time - current_time) >= (clk_period-1)) && 
     (($time - current_time) <= (clk_period+1)) );
endproperty : freq_chk

so we here we consider a tolerance limit in the clock period as +/-1. What would be the best method to have a tolerance percentage passed and the frequency checked accordingly.

I am looking at something like the one below (THIS DOES NOT WORK, just for demonstration of what I am looking at.)

property freq_chk_with_tol (time clk_period , bit disable_chk=0, int tolerance=0);
  time current_time; 
  disable iff ( disable_chk )
  ('1, current_time = $time) |=> 
   ( (($time - current_time) >= ( (clk_period * (1 - (tolerance/100) )) - 1)) && 
     (($time - current_time) <= ( (clk_period * (1 + (tolerance/100) )) + 1)) );
endproperty : freq_chk_with_tol

What would be the best method to check the frequencies of clocks that has a +/- tolerance % ?


Solution

  • As Greg suggested, changing the integer values to real did the trick for me.

    Below is the working code.

    property freq_chk_tol (time clk_period , bit disable_chk=0, real tolerance=0.00);
      time current_time; 
      disable iff ( disable_chk )
      ('1, current_time = $time) |=> 
       ( (($time - current_time) >= ( (clk_period * (1 - (tolerance/100.00) )) - 1)) && 
         (($time - current_time) <= ( (clk_period * (1 + (tolerance/100.00) )) + 1)) );
    endproperty : freq_chk_tol