Syntax error near "Architecture" in vhdl

Question

I'm trying to write a code in xilinx ise 14.7 and vhdl programming language using structural architecture. I have a vhdl module named mux_xor and a top down module named Q1. I get this error in Q1 top down module:

Line 62: Syntax error near "Architecture". My Q1 vhdl module code is as below: entity Q1 is

generic(n : integer := 10);
port(
    A,B : in std_logic_vector(0 to N-1);
    C,D : in std_logic;
    F: out std_logic);
end Q1;

architecture STRUCT of Q1 is

  signal K: std_logic_vector(0 to n-1);
  signal S: std_logic_vector(0 to n -1);

  component mux_xor
    port(A,B,inK,inS: in std_logic;
    oK,oS: out std_logic);
  end component mux_xor;

begin

  first_mux: mux_xor port map(A(0),B(0),C,D,K(0),S(0));

  comp_gen:
    for i in 1 to n-1 generate
      new_mux : mux_xor port map(A(i), B(i), K(i-1), S(i-1),K(i), S(i));

  F<=K(N-1);

end Architecture;

Answer 1

Looking at the line: for i in 1 to n-1 generate, you need a matching end generate;, so the statement would look like:

for i in 1 to n-1 generate
  new_mux : mux_xor port map(A(i), B(i), K(i-1), S(i-1),K(i), S(i));
end generate;

It's probably worth you spending 5 minutes performing a basic google search for the syntax surrounding your error. These are very very basic mistakes.