Syntax error near "tmp" in vhdl

Question

I am trying to write a code for serial parallel conversion in Xilinx ise and VHDL language, but I get this error:

Line 57: Syntax error near "tmp".

My VHDL Code is as below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY STP IS
    GENERIC(n : INTEGER :=10);
    PORT(din, clk, s: in std_logic; dout: out std_logic_vector(n-1 downto 0));
END STP;

ARCHITECTURE BEHAV OF STP IS

    Signal tmp : std_logic_vector(n-1 downto 0);
    Signal c : INTEGER := 0;

BEGIN

    PROCESS(s, clk)
    BEGIN
        IF (s'event AND s = '1' AND clk'event AND clk = '1' AND c = n) THEN
            tmp(c) <= din;
            dout <= tmp;
            c <= 0;
        ELSEIF(s'event AND s = '1' AND clk'event AND clk = '1')
            tmp(c) <= din;
            c <= c +1;
        ELSE
        END IF;

    END PROCESS;

END BEHAV;

Can somebody help me to handle this error?

Answer 1

You forgot about THEN in line ELSEIF(s'event AND s = '1' AND clk'event AND clk = '1').

There should also be ELSIF instead of ELSEIF. And actually, in this case there should be no such line, because your process can only have one statement sensitive on clock edge.