I want to find what control signals are used and what their values are for an R-type instruction for a multi-cycle processor, particularly in the fetch stage.
I deduced the following. In the F-stage, we have to fetch the instruction and increment the program counter.
To fetch the instruction, we have to access memory. However, the control signal table for R-type instructions show 0 for memRead and memWrite. Hence, I'm not sure what control signal should be asserted to fetch instruction.
In Pattterson and Henessey's textbook on Computer Organization, it notes that "controls signals to read instruction memory" should be asserted.
My questions are the following:
In multi cycle processor the instruction memory and data memory are combined and of course that control signals for memWrite and memRead are 0 and IRWrite is asserted during fetch step.
According to Harris & Harris the first step for any instruction is to fetch the instruction from memory at the address held in the PC.
The FSM enters this state on reset.
To read memory, IorD = 0, so the address is taken from the PC. IRWriteis asserted
to write the instruction into the instruction register, IR. Meanwhile, the PC
should be incremented by 4 to point to the next instruction. Because the
ALU is not being used for anything else, the processor can use it to compute
PC + 4 at the same time that it fetches the instruction.
ALUSrcA = 0, so
SrcA comes from the PC. ALUSrcB = 01, so SrcB is the constant 4.
ALUOp = 00, so the ALU decoder produces ALUControl = 010 to make
the ALU add. To update the PC with this new value, PCSrc = 0, and
PCWrite is asserted.
Control signals during Fetch step.
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite = aseerted
PCWrite = asserted