ARM; Performance Monitor Unit (PMU); Access th/ memory mapped registers;

Question

I'm trying to work with PMU module on ARM Cortex-A9. PMU could be controlled over 'CP15 interface' or through memory-map registers. I need the latter one.

"ARM® Cortex®‑A9 MPCore Technical Reference Manual" states

You can access the PMU counters, and their associated control registers through the internal CP15 interface, and through the APB, using the relevant offset when PADDRDBG[12]=1

Well, how to read/write this PADDRDBG register?

It seems that register is a part of 'CoreSight' module. Still could not find is it accessed th/ some CPxx interface or it's memory-mapped?

Any ideas? thanks.

PS: 'cp15' works fine, but I need memory access.

Answer 1

Looks like this is a signal on the core not something in address space possible the chip vendor has made a register for this so you have to look there, otherwise it is a compile time option (for the ARM core). what chip is this?