In my work I have to prove that the synthesized C++ visual algorithm code in VHDL (made via Vivado HLS) running on FPGA part on Zynq702 from Xilinx is quicker then classic C++ code on conventional CPU.
The main problem witch I am not able to resolve is - how is possible to "load" the synthesized code into SDK tool from Vivado 2016 tool, in other words - how is possible to run the synthesized VHDL code (bitstream) on the board?
In my opinion, the SDK program is only for C / C++ code. Is there any way how can I get the bitstream of VHDL code on the processor and prove that the synthesized code running on FPGA is quicker then the original C++ code?
Can you give me an advise ? I went through several YouTube tutorials and forums but it didn't help me.
Basically you need two versions of your code. One C/C++ version meant to run on the CPU and a version in C/C++ (slightly adapted) to use with HLS (targeting programmable logic) .
Xilinx offers a tool named SDSoC which does that for you. Basically you write your application once in C/C++. A profiler tells you which function uses most computational power and you can mark these functions to be off-loaded to programmable logic. The tool will use Vivado HLS in the background to convert your C/C++ to RTL code. SDSoC will tell you what the expected speedup is compared to the original code which runs entirely in the CPU.
I would suggest you to read through UG1028