It is over 2 weeks I faced a probem, Im programming an artix 7 FPGA. The process is simple:
when I add demux module to the whoe design, during the simulation I receive this Error: FATAL_ERROR: Iteration limit 10000 is reached.
The code for demux is here:
PUF_STATE_PROCESS:process(clk,uart_read,PUF_signal,UART_READ_FLAG)
begin
if (rising_edge(clk)) then
if (uart_read="11111111") then-- this means reset
stop_s<='0';
puf_signal<=initial;
reset_s<='1';
LED_S<="1111";
else
case puf_signal is
When initial=>
reset_s<='1';
puf_en_s<=(others=>'0');
LED_S<="0001";
--if UART_READ_FLAG='1' then
if uart_read/="11111110" then
else
stop_s<='0';
puf_signal<=ch_i;
end if;
-- end if;
When ch_i =>
if UART_READ="11111110" or UART_READ="11111111" then
else
ch_i_s<=(uart_read);
puf_signal<=ch_j;
LED_S<="0010";
end if;
when ch_j=>
if UART_READ="11111110" or UART_READ="11111111" or uart_read=ch_i_s then
else
ch_j_s<=(uart_read);
mux_en_s_j<=uart_read;
puf_signal<=start;
timer_s<=(others=>'0');
LED_S<="0011";
end if;
when start=>
reset_s<='0';
if timer_start<10000 then
mux_en_s_i<=ch_i_s;
mux_en_s_j<=ch_j_s;
timer_start<=timer_start+1;
for i in 0 to (RO_Number) loop
if i=ch_i_s then
puf_en_s(i)<='1';
elsif i=ch_j_s then
puf_en_s(i)<='1';
else
puf_en_s(i)<='0';
end if;
end loop;
LED_S<="0100";
else
puf_signal<=finish;
timer_start<=0;
LED_S<="0101";
end if;
when finish=>
if timer_s<timer_max_value then
timer_s<=timer_s+'1';
puf_en_s<=(others=>'0');
LED_S<="0100";
else
stop_s<='1';
timer_s<=(others=>'0');
LED_S<="0111";
puf_signal<=initial;
end if;
end case;
end if;
end if;
end process;
Can anyone tel me what is wrong with my code? i tested severa different approaches but I have this error.
Thanks
The main problem was not in this code.It was actually correlated to the Ring oscillators.In Ring Oscillators there was combinational loops with zero delay and it caused this problem