I'm actually studying into the MicroBlaze micro controller system that I've implemented in my FPGA. But I want to understand how is working this MCU. Let's consider this block diagram :
We can see that the processor is connect though 2 bus of 32 bits into a BRAM module. One of these bus is the ILMB (Instruction Local Memory Bus) and the other is DLMB (Data Local Memory Bus). We can see that both are connect to different port of the BRAM Module. So there is my question : In an Harvard Architecture, the program instructions and the random access memory is not supposed to be separated ? When we generate the system with the Xilinx IP Core Generator, the memory size that we put in is the size for the program instructions, the RAM or both ?
I've searched into the define in the xparameters.h header file to find the adress in memory of the ILMB and the DLMB and I've found that both are the same adress range.
#define XPAR_DLMB_CNTLR_BASEADDR 0x00000000
#define XPAR_DLMB_CNTLR_HIGHADDR 0x00003FFF
#define XPAR_ILMB_CNTLR_BASEADDR 0x00000000
#define XPAR_ILMB_CNTLR_HIGHADDR 0x00003FFF
The fact that both Instruction and Data are referred at the same adress confused me. Can someone tell me where I'm wrong ?
Both ILMB and DLMB buses in this case are sharing the same physical memory space. The same applies to the memory size parameter. By default Mircoblaze system is configured to have shared data and instruction memory space.
But the fact there are 2 separate busses allows you to configure your system to have data and instructions residing in totally different address spaces (or physical devices). For example, ILMB can be configured to address on a ROM memory and data can access completely different hardware block of RAM memory.
Microblaze is highly configurable CPU, and separate memory busses is one of these configuration points that needs to be configured in very rare cases. Most of the time these share the same address space of the BRAM memory.