How are breakpoint read/write implemented? Note that this is different from breakpoint execute.
The idea is to start off with a data memory address and then find the assembly instruction(s) which read/write from/to that address. In theory, we would have to check the registers and the next instruction being executed (taking into account displacement offsets) in order to find out whether this is true. Let's say the current instruction is a "store word": stw r0, 4 (r31) so it writes to address r31 + 4. We can find out whether this breaks by reading the value in r31, adding 4 and checking if this is equal to the initial data address.
However, this seems infeasible since with C programming you cannot monitor every instruction execution in assembly I believe. How is this being done in general or specific to PowerPC? Are there any special assembly instructions or debug registers which simplify this?
In the PowerPC, like all other CPUs that have such a feature, this is done with hardware support. There is a special register "Data Address Breakpoint" (DABR), where you can set which memory address that should be checked and if it should be read and/or write access etc.
The CPU will then trigger an interrupt (Data Storage Interrupt) when certain instructions performs reads or writes to that given address. From the ISR, you merely need to check the return address to see how you ended up there, and then you got the program address of the instruction that caused the break.
For details, check the PowerISA manual. (Their site http://www.power.org/ appears to be down atm)